This disclosure relates generally to the area of handshaking-based pipeline architectures and to other pipeline architectures with latch controllers.
The core of a field-programmable gate array (FPGA) consists of programmable logic components including lookup tables (LUTs) and flip-flops, as well as “hard” components such as IOs, memories, and DSP blocks. Conventionally, these have been used to build cycle-accurate pipelined machines. As performance targets increase, these machines become more and more pipelined in order to meet the increased operating frequency (i.e. decreased cycle time) requirements. The pipelines make use of register stages that pass data from one stage to the next, with latch controllers in between the registers that determine when data is to pass from one stage to the next.
As will be explained in greater detail below, in a handshaking-based pipeline, data transfers may be synchronized using latch controllers that send forward-going request events and reverse-going acknowledgment events using a bidirectional inter-stage control wire, to which the controllers are attached. The simple and fast implementation may include a “keeper” device attached to the bidirectional wire to retain the state of the wire in between events (retain the state when neither the sender is announcing new data nor the receiver is announcing the consumption of the data). However, these keeper devices “fight” new events and cause contention on the bidirectional wire. In addition, the keeper devices may create issues during layout of the device on which they reside, and the keeper devices may also increase crowbar current.
A handshaking-based pipeline allows data to progress forward at a locally appropriate rate, using what may be in effect locally-generated clocks for each register stage. Thus, it does not require low-skew globally-distributed clocks. Instead, adjacent stages communicate using forward-going request signals and reverse-going acknowledge signals, using one of two basic protocols. In the two-phase protocol, any transition on request indicates data is available, and any transition on acknowledge indicates the data has been consumed. In the four-phase protocol, a HIGH signal on request indicates data is available, and a subsequent HIGH signal on acknowledge indicates the data has been consumed. This cycle is repeated for a LOW signal (i.e., a LOW signal on request and a subsequent LOW signal on acknowledge) before the next data can flow forward. The two-phase protocol has the advantage of half the round-trip handshakes as the four-phase protocol. However, the four-phase protocol is level-sensitive, which results in simpler circuitry than the two-phase protocol.
The two-phase protocol and the four-phase protocol may be combined into a hybrid protocol, which may be used with a single wire. In this single-wire protocol, the producer (the pipeline stage producing data) raises a bidirectional request/acknowledge signal HIGH to indicate new data is available, and then the consumer (the pipeline stage consuming data) lowers the signal to indicate that the data has been consumed. Unfortunately, when neither producer nor consumer forces the state of the request/acknowledge signal, the producer and the consumer should each remember its previous state. Thus, a full latch “keeper” device may be required that will remember the previous state of the producer and consumer and that will contend against drivers that may be active. There may be difficulty in determining where such a keeper device may be placed. For example, the keeper device may be placed in the middle of the producer and consumer, which may require the use of a separate island of transistors. As another example, the keeper device may be placed by one of the consumer or the producer, which may result in a skewed response during the transitions in state of either the producer or the consumer. Thus, it would be desirable to have a controller/keeper device that avoids contention (e.g. with drivers) and one that provides a balanced response during transitions in pipeline stage states.